One often needs to derive from an asynchronous input to an FPGA a synchronous clock-enable pulse just one clock long to ensure that the appropriate event to be triggered by the input always takes place, and just once, for each trigger.  At the sacrifice of just one flip-flop being clocked asynchronously this circuit has several advantages over the standard all-synchronous method.  Firstly, the minimum length of the trigger pulse just has to exceed the minimum clock pulse width of the flip-flop (1.4ns for a Spartan IIE) and is independent of the synchronous clock frequency whereas the usual approach needs at least one clock period plus the set-up/hold time, 6ns at 250MHz  but increasing with the clock period.  Secondly, the synchronous pulse starts on the first clock that meets the set-up condition, whereas if a truly synchronous pulse is required the standard approach requires a further clock delay.

schematic

Here is the VHDL code corresponding to the schematic:


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity JustOne is
port (
Trigger : in std_logic;
Clock : in std_logic;
Pulse : out std_logic
);
end JustOne;

architecture J1 of JustOne is
signal QA: std_logic := '0';
signal QB: std_logic := '0';

begin
Pulse <= QB;
process (Trigger, QB)
begin
if QB='1' then
QA <= '0';
elsif (Trigger'event and Trigger='1') then
QA <= '1';
end if;
end process;

process (Clock)
begin
if Clock'event and Clock ='1' then
QB <= QA;
end if;
end process;

end J1;